A semiconductor chip is generally connected to an external circuit element through contacts on the front face of the chip. The contacts may be disposed in an area array, which substantially covers the entire front face of the chip, or in elongated rows extending parallel to and adjacent each edge of the chip. In certain embodiments, the contacts are connected to the external circuit element using flexible leads or wires. For example, in the tape automated bonding process (hereinafter referred to as the "TAB" process), a dielectric sheet, such as a thin foil of polyimide, is provided with one or more bonding windows and an array of metallic leads is provided on one surface of the dielectric sheet. Each lead extends outwardly from a central portion of the dielectric sheet towards one of the bond windows and has an outermost end projecting beyond the edge of the bond window. The dielectric sheet is juxtaposed with the chip so that the bond windows are aligned with the chip and so that the outermost ends of the leads will extend over the front, contact bearing face of the chip. The outermost ends of the leads are then bonded to the contacts of the chip, as by ultrasonic or thermocompression bonding. The inner ends of the leads are connected to external circuit elements, such as a printed circuit board, via conductive terminals.
Certain designs have reduced the stress on such electrical connections by redistributing the thermal cycling stress into a portion of the semiconductor chip package itself. An example of such a design is shown in commonly assigned U.S. Pat. Nos. 5,148,265 and 5,148,266, both disclosures of which are incorporated herein by reference. One disclosed embodiment of these patents shows the use of a chip carrier in combination with a resilient element to minimize problems associated with thermal cycling. Typically, the resilient element includes an elastomeric layer which, in the finished package, is disposed between the chip carrier and the contact bearing surface of the semiconductor chip. The resilient element provides resiliency to individual terminals on the chip carrier, allowing each terminal to move in relation to its electrically connected chip contact to accommodate for thermal cycling differences as necessary during testing, final assembly and operation of the device.
It has been determined that the use of an encapsulating material around the resilient element further reduces the stress on the electrical connections between the semiconductor chip and a chip carrier during operation of the chip and seals the elements of the chip package against corrosion. For example, copending, commonly assigned U.S. Pat. No. 5,659,952, the disclosure of which is incorporated herein by reference, discloses a method of fabricating a compliant interface for a semiconductor chip typically comprised of a compliant encapsulation layer having a controlled thickness. In certain preferred embodiments of the '952 Patent, a first support structure, such as a flexible, substantially inextensible dielectric film, is provided. A resilient element, such as a plurality of compliant pads defining channels therebetween, is attached to a first surface of the first support structure. The compliant pad/support structure subassembly is then assembled with a second microelectronic element such as a semiconductor chip having a front face including a plurality of contacts. During assembly, the front face of the semiconductor chip is abutted against the compliant pads and the contacts are electrically connected to corresponding terminals on a second side of the dielectric film. An encapsulant material, such as a curable liquid elastomer, is then disposed between the semiconductor chip and the dielectric film and around the compliant pads while the chip and the dielectric film are held in place.
Other methods of encapsulating a microelectronic package are disclosed in commonly assigned U.S. patent application Ser. No. 08/726,697 filed Oct. 7, 1996, the disclosure of which is incorporated by reference herein. According to the '697 application, a semiconductor chip package assembly has a spacer layer between the top surface of a sheet-like substrate and the contact bearing surface of a semiconductor chip. The substrate has conductive leads thereon and the leads have first ends which are electrically connected to terminals on the substrate and second ends which are bonded to respective chip contacts. Typically, the spacer layer includes a compliant or elastomeric material. A protective layer is attached on a bottom surface of the substrate so as to cover the terminals on the substrate and to seal any apertures in the substrate. After the attachment of the protective layer, a flowable, curable encapsulant material is deposited around at least a portion of a periphery of the semiconductor chip so as to encapsulate the leads. The protective layer prevents the encapsulant from flowing through any substrate apertures. The encapsulant material is then cured or at least partially cured to allow for handling or further processing.
Commonly assigned U.S. patent application Ser. No. 08/532,235 filed Sep. 22, 1995, the disclosure of which is incorporated herein by reference, provides methods of encapsulating a plurality of microelectronic assemblies. Each microelectronic assembly includes a dielectric layer overlying a microelectronic element, such as a semiconductor chip, and having a top surface facing away from the microelectronic element. Each assembly also includes terminals on a top surface of the dielectric layer and flexible leads connecting the terminals to contacts on the microelectronic element. The assemblies are disposed side-by-side with one another so that the microelectronic elements are side-by-side and so that the dielectric layers are also disposed side-by-side in substantially co-planar relationship with one another. The dielectric layers of the various assemblies may be separate from one another and may define openings therebetween. The dielectric layers of the various subassemblies may further have openings through the dielectric layer. The disclosed method further includes the step of filling a curable liquid encapsulant between the dielectric layers and the microelectronic elements while substantially preventing flow of the encapsulant onto the top surfaces of the dielectric layers through the openings defined between and/or within the dielectric layers. In preferred embodiments, a top covering layer, such as a substantially imperforate layer, is applied over the top surfaces of the respective dielectric layers and occludes the openings between and/or within the dielectric layers. Thus, the top covering layer serves to prevent flow of the encapsulant onto the top surfaces during the encapsulating step. After the filling step, the encapsulant is preferably cured to a gel or a solid and most preferably to a compliant gel or solid. The top covering layer may then be removed. Alternatively, the top covering layer may remain as an integral part of the assembly. Preferably the step of providing the top covering layer includes the step of providing a solid layer and a layer of a soft sealant so that the sealant is disposed between the solid layer and the dielectric layers of the various assemblies. The sealant substantially encapsulates the terminals. The sealant may be an adhesive and may secure the solid layer to the assemblies.
Accordingly, a method of controlling the encapsulation process so that the terminals on an exterior surface of a semiconductor chip package are not contaminated is desirable. In addition, it would be desirable to provide a method of forming an efficacious compliant layer between the microelectronic elements.